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1 features ? utilizes the avr ? risc architecture ? avr ? high-performance and low-power risc architecture ? 90 powerful instructions ? most single clock cycle execution ? 32 x 8 general-purpose working registers ? up to 4 mips throughput at 4 mhz ? nonvolatile program memory ? 2k bytes of flash program memory ? endurance: 1,000 write/erase cycles ? programming lock for flash program data security ? peripheral features ? interrupt and wake-up on low-level input ? one 8-bit timer/counter with separate prescaler ? on-chip analog comparator ? programmable watchdog timer with on-chip oscillator ? built-in high-current led driver with programmable modulation ? special microcontroller features ? low-power idle and power-down modes ? external and internal interrupt sources ? power-on reset circuit with programmable start-up time ? internal calibrated rc oscillator ? power consumption at 1 mhz, 2v, 25 c ? active: 3.0 ma ? idle mode: 1.2 ma ? power-down mode: <1 a ? i/o and packages ? 11 programmable i/o lines, 8 input lines and a high-current led driver ? 28-lead pdip, 32-lead tqfp, and 32-pad mlf ? operating voltages ?v cc : 1.8v - 5.5v for the attiny28v ?v cc : 2.7v - 5.5v for the attiny28l ? speed grades ? 0 - 1.2 mhz for the attiny28v ? 0 - 4 mhz for the attiny28l pin configurations pdip reset pd0 pd1 pd2 pd3 pd4 vcc gnd xtal1 xtal2 pd5 pd6 pd7 (ain0) pb0 pa0 pa1 pa3 pa2 (ir) pb7 pb6 gnd nc vcc pb5 pb4 (int1) pb3 (int0) pb2 (t0) pb1 (ain1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 tqfp/qfn/mlf 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 pd3 pd4 nc vcc gnd nc xtal1 xtal2 pb7 pb6 nc gnd nc nc vcc pb5 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 pd5 pd6 pd7 (ain0) pb0 (ain1) pb1 (t0) pb2 (int0) pb3 (int1) pb4 pd2 pd1 pd0 reset pa0 pa1 pa3 pa2 (ir) 8-bit microcontroller with 2k bytes of flash attiny28l attiny28v summary rev. 1062fs?avr?07/06 note: this is a summary do cument. a complete document is available on our web site at www.atmel.com.
2 attiny28l/v 1062fs?avr?07/06 description the attiny28 is a low-power cmos 8-bit microcontroller based on the avr risc archi- tecture. by executing powerful instructions in a single clock cycle, the attiny28 achieves throughputs approaching 1 mips per mhz, allowing the system designer to optimize power consumption versus processing speed. the avr core combines a rich instruction set with 32 general-purpose working registers. all the 32 registers are directly con- nected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architec- ture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. block diagram figure 1. the attiny28 block diagram the attiny28 provides the following features: 2k bytes of flash, 11 general-purpose i/o lines, 8 input lines, a high-current led driver, 32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable watchdog timer with internal oscillator and 2 software-select able power-saving modes. the idle mode stops the cpu while allowing the time r/counter and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. the wake-up or inter- program counter internal oscillator watchdog timer stack pointer program flash mcu control register general purpose registers instruction register timer/ counter instruction decoder data register portb programming logic timing and control interrupt unit status register alu portb vcc gnd control lines + - analog comparator 8-bit data bus z oscillator portd data register porta porta porta control register xtal2 xtal1 reset hardware stack data register portd data dir reg. portd hardware modulator internal calibrated oscillator
3 attiny28l/v 1062fs?avr?07/06 rupt on low-level input feature enables the attiny28 to be highly responsive to external events, still featuring the lowest power co nsumption while in th e power-down modes. the device is manufactured using atmel?s hi gh-density, nonvolatile memory technology. by combining an enhanced risc 8-bit cpu with flash on a monolithic chip, the atmel attiny28 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. the attiny28 avr is supported with a full suite of program and system developm ent tools including: macro assemblers, pro- gram debugger/simulators, in-circuit emulators and evaluation kits. pin descriptions vcc supply voltage pin. gnd ground pin. port a (pa3..pa0) port a is a 4-bit i/o port. pa2 is output-only and can be used as a high-current led driver. at v cc = 2.0v, the pa2 output buffer can sink 25 ma. pa3, pa1 and pa0 are bi-directional i/o pins with internal pull-ups (s elected for each bit). the port pins are tri- stated when a reset condition becomes active, even if the clock is not running. port b (pb7..pb0) port b is an 8-bit input port with internal pull-ups (selected for all port b pins). port b pins that are externally pulled low will sour ce current if the pu ll-ups are activated. port b also serves the functions of various special features of the attiny28 as listed on page 27. if any of the special features are enabled, the pull-up(s) on the corresponding pin(s) is automatically disabled. the por t pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d (pd7..pd0) port d is an 8-bit i/o port. port pins can pr ovide internal pull-up resistors (selected for each bit). the port pins are tri-stated when a reset condition becomes active, even if the clock is not running. xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. xtal2 output from the invert ing oscillator amplifier. reset reset input. an external reset is generated by a low level on the reset pin. reset pulses longer than 50 ns will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset.
4 attiny28l/v 1062fs?avr?07/06 notes: 1. for compatibility with future devices, reserved bits shoul d be written to zero if accessed. reserved i/o memory address es should never be written. 2. some of the status flags are cleared by writing a logical ?1 ? to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions wo rk with registers $00 to $1f only. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page $3f sreg i t h s v n z c page 6 $3e reserved ... reserved $20 reserved $1f reserved $1e reserved $1d reserved $1c reserved $1b porta - - - - porta3 porta2 porta1 porta0 page 32 $1a pacr - - - - dda3 pa2hc dda1 dda0 page 32 $19 pina - - - -pina3 - pina1 pina0 page 32 $18 reserved $17 reserved $16 pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 32 $15 reserved $14 reserved $13 reserved $12 portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 page 33 $11 ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 page 33 $10 pind pind7 pind6 pind5 pind 4 pind3 pind2 pind1 pind0 page 33 $0f reserved $0e reserved $0d reserved $0c reserved $0b reserved $0a reserved $09 reserved $08 acsr acd -acoaciacie - acis1 acis0 page 44 $07 mcucs plupb - se sm wdrf - extrf porf page 19 $06 icr int1 int0 llie toie0 isc11 isc10 isc01 isc00 page 22 $05 ifr intf1 intf0 -tov0 - - - - page 23 $04 tccr0 fov0 - - oom01 oom00 cs02 cs01 cs00 page 35 $03 tcnt0 timer/counter0 (8-bit) page 36 $02 modcr ontim4 ontim3 ontim2 ontim1 ontim0 mconf2 mconf1 mconf0 page 43 $01 wdtcr - - - wdtoe wde wdp2 wdp1 wdp0 page 37 $00 osccal oscillator calibration register page 9
5 attiny28l/v 1062fs?avr?07/06 instruction set summary mnemonic operands description operation flags # clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd $ff - rd z,c,n,v 1 neg rd two?s complement rd $00 - rd z,c,n,v,h 1 sbr rd, k set bit(s) in register rd rd v k z,n,v 1 cbr rd, k clear bit(s) in register rd rd ? (ffh - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd - 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 rcall k relative subroutine call pc pc + k + 1 none 3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd, rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2 cp rd, rr compare rd - rr z,n,v,c,h 1 cpc rd, rr compare with carry rd - rr - c z,n,v,c,h 1 cpi rd, k compare register with immediate rd - k z n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1/2 sbrs rr, b skip if bit in regist er is set if (rr(b) = 1) pc pc + 2 or 3 none 1/2 sbic p, b skip if bit in i/o register cleared if (p(b) = 0) pc pc + 2 or 3 none 1/2 sbis p, b skip if bit in i/o register is set if (p(b) = 1) pc pc + 2 or 3 none 1/2 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v = 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v = 1) then pc pc + k + 1 none 1/2 brhs k branch if half-carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half-carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t-flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t-flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1/2
6 attiny28l/v 1062fs?avr?07/06 data transfer instructions ld rd, z load register indirect rd (z) none 2 st z, rr store register indirect (z) rr none 2 mov rd, rr move between registers rd rr none 1 ldi rd, k load immediate rd knone1 in rd, p in port rd pnone1 out p, rr out port p rr none 1 lpm load program memory r0 (z) none 3 bit and bit-test instructions sbi p, b set bit in i/o register i/o(p,b) 1none2 cbi p, b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c, rd(n+1) rd(n), c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c, rd(n) rd(n+1), c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n = 0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4), rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear zero flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two?s complement overflow v 1v1 clv clear two?s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half-carry flag in sreg h 1h1 clh clear half-carry flag in sreg h 0h1 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 instruction set summary (continued) mnemonic operands description operation flags # clocks
7 attiny28l/v 1062fs?avr?07/06 notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging alternative, complies to the european dire ctive for restriction of hazardous substances (rohs direc- tive).also halide free and fully green. ordering information speed (mhz) power supply (volts) ordering code package (1) operation range 4 2.7 - 5.5 attiny28l-4ac attiny28l-4pc attiny28l-4mc 32a 28p3 32m1-a commercial (0 c to 70 c) attiny28l-4ai attiny28l-4au (2) attiny28l-4pi attiny28l-4pu (2) attiny28l-4mi attiny28l-4mu (2) 32a 32a 28p3 28p3 32m1-a 32m1-a industrial (-40 c to 85 c) 1.2 1.8 - 5.5 attiny28v-1ac attiny28v-1pc attiny28v-1mc 32a 28p3 32m1-a commercial (0 c to 70 c) attiny28v-1ai attiny28v-1au (2) attiny28v-1pi attiny28v-1pu (2) attiny28v-1mi attiny28v-1mu (2) 32a 32a 28p3 28p3 32m1-a 32m1-a industrial (-40 c to 85 c) package type 32a 32-lead, thin (1.0 mm) plastic quad flat package (tqfp) 28p3 28-lead, 0.300" wide, plastic dual inline package (pdip) 32m1-a 32-pad, 5x5x1.0 body, lead pitch 0.50mm, quad flat no-lead/micr o lead frame package (qfn/mlf)
8 attiny28l/v 1062fs?avr?07/06 packaging information 32a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32a, 32-lead, 7 x 7 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 32a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b notes: 1. this package conforms to jedec reference ms-026, variation aba. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 8.75 9.00 9.25 d1 6.90 7.00 7.10 note 2 e 8.75 9.00 9.25 e1 6.90 7.00 7.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ common dimensions (unit of measure = mm) symbol min nom max note
9 attiny28l/v 1062fs?avr?07/06 28p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28p3 , 28-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) b 28p3 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb b2 (4 places) common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.5724 a1 0.508 ? ? d 34.544 ? 34.798 note 1 e 7.620 ? 8.255 e1 7.112 ? 7.493 note 1 b 0.381 ? 0.533 b1 1.143 ? 1.397 b2 0.762 ? 1.143 l 3.175 ? 3.429 c 0.203 ? 0.356 eb ? ? 10.160 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
10 attiny28l/v 1062fs?avr?07/06 32m1-a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 3 2m1-a , 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0.50 mm, e 32m1-a 5/25/06 3.10 mm exposed pad, micro lead frame package (mlf) common dimen s ion s (unit of measure = mm) s ymbol min nom max note d1 d e1 e e b a3 a2 a1 a d2 e2 0.08 c l 1 2 3 p p 0 1 2 3 a 0.80 0.90 1.00 a1 ? 0.02 0.05 a2 ? 0.65 1.00 a3 0.20 ref b 0.18 0.23 0.30 d d1 d2 2.95 3.10 3.25 4.90 5.00 5.10 4.70 4.75 4.80 4.70 4.75 4.80 4.90 5.00 5.10 e e1 e2 2.95 3.10 3.25 e 0.50 bsc l 0.30 0.40 0.50 p ? ? 0.60 ? ? 12 o note: jedec standard mo-220, fig. 2 (anvil singulation), vhhd-2. top view s ide view bottom view 0 pin 1 id pin #1 notch (0.20 r) k 0.20 ? ? k k
11 attiny28l/v 1062fs?avr?07/06 errata all revisions no known errata.
12 attiny28l/v 1062fs?avr?07/06 datasheet revision history please note that the referring page numbers in this section are referred to this docu- ment. the referring revision in this section are referring to the document revision. rev ? 01/06g 1. updated chapter layout. 2. updated ?ordering information? on page 7. rev ? 01/06g 1. updated description for ?port a? on page 25. 2. added note 6 in ?dc characteristics? on page 54. 3. updated ?ordering information? on page 7. 4. added ?errata? on page 11. rev ? 03/05f 1. updated ?electrical characteristics? on page 54. 2. mlf-package alternative changed to ? quad flat no-lead/micro lead frame package qfn/mlf?. 3. updated ?ordering information? on page 7.
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